//-----------------------------------------------------------------------------
//  Copyright (c) 2013 by HangZhou HenqgQiao Design Corporation. All rights reserved.
//
//  Project  : 
//  Module   : over sample the input data with 8-phases 311M clock
//  Parent   : 
//  Children : 
//
//  Description: 
//
//  Parameters:
//  Local Parameters:
//
//  Notes       : 
//
//  Multicycle and False Paths

module FRM_RSCRM1(
   input                         FRM_RESET,
   input                         FRM_RXCLK,

   input[8:0]                    RSCRM1_IN_FMCNT270,
   input[3:0]                    RSCRM1_IN_FMCNT9,
   input[7:0]                    RSCRM1_IN_DATA,
   input                         RSCRM1_IN_DEN,
   input                         RSCRM1_IN_OOF,

   output reg[7:0]               RSCRM1_OUT_DATA,
   output reg                    RSCRM1_OUT_DEN,
   output reg[8:0]               RSCRM1_OUT_FMCNT270,
   output reg[3:0]               RSCRM1_OUT_FMCNT9,
   output reg[3:0]               RSCRM1_OUT_B1ERR,
   output reg                    RSCRM1_OUT_B1ERR_EN
   );


reg[7:0]                         SCRM_VECTOR;
reg                              SCRM_EN;


reg[7:0]                         B1_CALCULATING;
reg[7:0]                         B1_RESULT;
reg[7:0]                         B1_ERR_VECTOR;

always @( RSCRM1_IN_FMCNT270 or RSCRM1_IN_FMCNT9) begin
   if ( RSCRM1_IN_FMCNT270[8:0] <9'd9 && RSCRM1_IN_FMCNT9[3:0]==4'd0 )
      SCRM_EN                                       <= 1'b0;
   else
      SCRM_EN                                       <= 1'b1;
end

always @( posedge FRM_RESET or posedge FRM_RXCLK ) begin
   if ( FRM_RESET==1'b1 )
      SCRM_VECTOR[7:0]                              <= 8'd0;
   else begin
      if ( RSCRM1_IN_FMCNT270[8:0]==9'd269 && RSCRM1_IN_FMCNT9[3:0]==4'd8 && RSCRM1_IN_DEN==1'b1)
         SCRM_VECTOR[7:0]                           <= 8'hfe;
      else if ( SCRM_EN==1'b1 && RSCRM1_IN_DEN==1'b1 ) begin
         SCRM_VECTOR[7]                             <= SCRM_VECTOR[6] ^ SCRM_VECTOR[5];
         SCRM_VECTOR[6]                             <= SCRM_VECTOR[5] ^ SCRM_VECTOR[4];
         SCRM_VECTOR[5]                             <= SCRM_VECTOR[4] ^ SCRM_VECTOR[3];
         SCRM_VECTOR[4]                             <= SCRM_VECTOR[3] ^ SCRM_VECTOR[2];
         SCRM_VECTOR[3]                             <= SCRM_VECTOR[2] ^ SCRM_VECTOR[1];
         SCRM_VECTOR[2]                             <= SCRM_VECTOR[1] ^ SCRM_VECTOR[0];
         SCRM_VECTOR[1]                             <= SCRM_VECTOR[0] ^ (SCRM_VECTOR[6] ^ SCRM_VECTOR[5]);
         SCRM_VECTOR[0]                             <= (SCRM_VECTOR[6] ^ SCRM_VECTOR[5]) ^ (SCRM_VECTOR[5] ^ SCRM_VECTOR[4]);
      end
   end
end

always @( posedge FRM_RESET or posedge FRM_RXCLK ) begin
   if ( FRM_RESET==1'b1 ) begin
      RSCRM1_OUT_DEN                                <= 1'b0;
      RSCRM1_OUT_FMCNT270[8:0]                      <= 9'd0;
      RSCRM1_OUT_FMCNT9[3:0]                        <= 4'd0;
      RSCRM1_OUT_DATA[7:0]                          <= 4'd0;
   end
   else begin
      RSCRM1_OUT_DEN                                <= RSCRM1_IN_DEN;
      RSCRM1_OUT_FMCNT270[8:0]                      <= RSCRM1_IN_FMCNT270[8:0];
      RSCRM1_OUT_FMCNT9[3:0]                        <= RSCRM1_IN_FMCNT9[3:0];
      if ( RSCRM1_IN_OOF==1'b1 )
         RSCRM1_OUT_DATA[7:0]                       <= 8'hff;
      else if ( SCRM_EN==1'b0 )
         RSCRM1_OUT_DATA[7:0]                       <= RSCRM1_IN_DATA[7:0];
      else
         RSCRM1_OUT_DATA[7:0]                       <= RSCRM1_IN_DATA[7:0] ^ SCRM_VECTOR[7:0];
   end
end




always @( posedge FRM_RESET or posedge FRM_RXCLK ) begin
   if ( FRM_RESET==1'b1 )
      B1_CALCULATING[7:0]                           <= 8'd0;
   else begin
      if ( RSCRM1_IN_FMCNT270[8:0]==9'd269 && RSCRM1_IN_FMCNT9[3:0]==4'd8 && RSCRM1_IN_DEN==1'b1 )
         B1_CALCULATING[7:0]                        <= 8'd0;
      else if ( RSCRM1_IN_DEN==1'b1 )
         B1_CALCULATING[7:0]                        <= B1_CALCULATING[7:0] ^ RSCRM1_IN_DATA[7:0];
   end
end

always @( posedge FRM_RESET or posedge FRM_RXCLK ) begin
   if ( FRM_RESET==1'b1 )
      B1_RESULT[7:0]                                <= 8'd0;
   else begin
      if ( RSCRM1_IN_FMCNT270[8:0]==9'd269 && RSCRM1_IN_FMCNT9[3:0]==4'd8 && RSCRM1_IN_DEN==1'b1 )
         B1_RESULT[7:0]                             <= B1_CALCULATING[7:0] ^ RSCRM1_IN_DATA[7:0];
   end
end

always @( posedge FRM_RESET or posedge FRM_RXCLK ) begin
   if ( FRM_RESET==1'b1 )
      B1_ERR_VECTOR[7:0]                            <= 8'd0;
   else begin
      if ( RSCRM1_OUT_FMCNT270[8:0]==9'd0 && RSCRM1_OUT_FMCNT9[3:0]==4'd1 && RSCRM1_OUT_DEN==1'b1 )
         B1_ERR_VECTOR[7:0]                         <= B1_RESULT[7:0] ^ RSCRM1_OUT_DATA[7:0];
   end
end

always @( posedge FRM_RESET or posedge FRM_RXCLK ) begin
   if ( FRM_RESET==1'b1 )
      RSCRM1_OUT_B1ERR[3:0]                          <= 4'd0;
   else
      RSCRM1_OUT_B1ERR[3:0]                          <= {3'd0, B1_ERR_VECTOR[0]} + {3'd0, B1_ERR_VECTOR[1]} + {3'd0, B1_ERR_VECTOR[2]} + {3'd0, B1_ERR_VECTOR[3]} + {3'd0, B1_ERR_VECTOR[4]} + {3'd0, B1_ERR_VECTOR[5]} + {3'd0, B1_ERR_VECTOR[6]} +{3'd0, B1_ERR_VECTOR[7]};
end
always @( posedge FRM_RESET or posedge FRM_RXCLK ) begin
   if ( FRM_RESET==1'b1 )
      RSCRM1_OUT_B1ERR_EN                            <= 1'b0;
   else
      RSCRM1_OUT_B1ERR_EN                            <= RSCRM1_IN_FMCNT9[3:0]==4'd2;
end

endmodule


